In a multiprocessor system, redundant configuration is generally adopted by providing a plurality of node controllers. Therefore, even at a failure time of one node controller, an operation of the system can be continued by another node controller in which no failure has occurred. Conventionally, in order to prevent the down of system performance at the failure time of the node controller, it is required to change many settings of an address decoder, a routing table and so on of each node. Therefore, it takes a long time until the operation of the system is recovered, and particularly, a time required for the change of the setting cannot sometimes satisfy constraints of the system when the operation is continued without rebooting the system.
Japanese Patent Publication (JP-A-Heisei 4-321138A: patent literature 1) discloses a multiprocessor system in which there is no need for application to execute a special process even at a time of degeneracy operation due to a failure. This multiprocessor system connects a plurality of processors assigned with continuous identification data, through communication node elements having communication route data. The communication node elements change a communication route to a processor in which a failure has been detected into a new communication route to a normal processor, as if the identification data of the plurality of processors are continuous and the total number of processors is constant. Therefore, according to the multiprocessor system according to the patent literature 1, there is no need to execute a process, considering continuity of the processors and the total number of processors at the time of degeneracy operation of the system.
Also, Japanese Patent Publication (JP-A-Heisei 5-158840: a patent literature 2) discloses a frame relay communication processing system in an inter-processor communication control system that allows communication between processors connected to a communication controller even if a failure has occurred in any of duplex communication controllers connected to configured a duplex ring. In this frame relay communication processing system, when the failure has occurred in the communication controller corresponding to a different processor in a communication control system of each system so that direct communication by the communication system in each system between processors becomes impossible, communication from one processor corresponding to the failure occurred communication controller to another processor is performed by relaying a frame from one system of the normal communication controller to another system through processors in which the communication controllers of both systems are in the normal state. According to the frame relay communication processing system according to the patent literature 2, communication down between the processors including the failure occurred communication controller can be prevented by relaying transmission/reception of the frame by the processors having the communication controllers in which both systems are in the normal state in the case of a duplex failure in the network such as a ring configuration of the duplex ring communication controllers.
Japanese Patent Publication (JP-A-Heisei 5-175980A: patent literature 3) discloses an inter-system cross connectible communication control system which can maintain communication through the same communication bus without performing system change-over even if a failure has occurred in a common bus, a channel controller or the like. In the inter-system cross connectible communication control system according to the patent literature 3, common bus interface units are duplexed in each communication controller of a 0 system and a 1 system. One common bus interface unit is connected to a self-system ring bus through a self-system ring bus interface unit. Also, the other common bus interface unit is connected to another-system ring bus through another-system ring bus interface unit. The ring bus interface unit in each system usually selects the common bus interface unit connected to the self-system common bus, and selects the common bus interface device connected to the common bus of the other system when a failure has occurred in the common bus of the self-system, and performs communication through the ring bus of the self-system. According to the inter-system cross connectible communication control system according to the patent literature 3, even if the failure has occurred in the common bus of an active system, as long as the unit connected to the communication bus is in the normal state, communication can be continuously performed without changing over the system of the communication bus, by performing inter-system cross connectible communication with the other system.
Japanese Patent Publication (JP-A-Heisei 11-053331: a patent literature 4) discloses a distributed memory type multiprocessor system in which sufficient countermeasures for failure avoidance are taken to improve an operation rate of the system as a whole. In the distributed memory type multiprocessor system according to the patent literature 4, a plurality of processor configuration units, in each of which processors and local memories are connected by a local network, are connected by a global network to be mutually communicable. The processor configuration unit includes an I/O processor having an input/output function connected to a processor, a channel unit connected to the I/O processor, and a request transmission unit for degeneracy operation connected to the I/O processor and a bus. According to the distributed memory type multiprocessor system according to the patent literature 4, when the failure has occurred between the processor configuration unit and the global network, if there is no any failure in hardware in the processor configuration unit, sufficient failure countermeasures are taken so that the operation rate of the whole system can be improved without degenerating the failure occurred processor configuration unit while data transfer rate is reduced.
Citation List
                Patent Literature 1: JP-A-Heisei 4-321138        Patent Literature 2: JP-A-Heisei 5-158840        Patent Literature 3: JP-A-Heisei 5-175980        Patent Literature 4: JP-A-Heisei 11-053331        